1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that corrects defective data stored in a read only memory (ROM) by using redundant data.
2. Description of Related Art
In some semiconductor devices, a defective element may occur during a manufacturing process, which causes a deterioration in yield. In particular, the recent increase in capacity of semiconductor memory devices makes it necessary to determine a chip containing a defective memory cell among a large number of cells, as a defective product. For this reason, in semiconductor memory devices, a predetermined number of defects are relieved using error correction techniques such as parity check and error correcting code (ECC), thereby preventing a deterioration in yield.
The error correction technique using the parity check is effective when the position of a bit error contained in data can be specified in advance. According to the error correction technique using the parity check, a calculation is performed to determine that the number of “1” or “0” bits included in the data is even or odd, and 1-bit parity data is generated. Then, the number of “1” or “0” bits included in the read data is calculated, and when the result obtained by the calculation does not match the parity data, the bit error specified in advance is inverted and output.
Meanwhile, the error correction technique using the ECC is effective when the position of a defect is not specified. According to the error correction technique using the ECC, an operation is carried out using parity data having a plurality of bits and data to be processed, so that the bit error present at an unspecified position can be corrected.
In this regard, Japanese Unexamined Patent Application Publication No. 2-203500 (Araki) discloses the error correction technique using the parity check. Further, Japanese Unexamined Patent Application Publication No. 2007-141364 (Sato) discloses the error correction technique using the ECC.
FIG. 4 shows a block diagram of a semiconductor memory device disclosed by Araki. As shown in FIG. 4, the semiconductor memory device disclosed by Araki includes a memory cell array 100, terminals 110, 120, 180, and 201 to 2016, a row decoder 130, a column decoder/sense amplifier 140, a data correcting section 150, a parity check circuit 160, a defective output memory 170, and out buffers 191 to 1916. The memory cell array 100 includes a data section 100a and a parity section 100b. The data section 100a stores data to be stored in the semiconductor memory device. The parity section 100b stores, in each row, a parity code generated based on data stored in each row of the data section 100a. 
Further, the semiconductor memory device disclosed by Araki performs parity check in the parity check circuit 160 based on the data read out from the data section 100a and the parity code read out from the parity section 100b. The defective output memory 170 stores in advance the position in the column direction of the bit error occurring in the read data. The data correcting section 150 includes data correcting circuits 151 to 1516 respectively corresponding to the pieces of data read out from the data section 100a. Further, in the data correcting section 150, the data correcting circuit corresponding to the position in the column direction, at which the bit error occurs and which is stored in the defective output memory 170, corrects the data using the parity check result generated by the parity check circuit 160. The position is stored in the defective output memory 170. In the semiconductor memory device disclosed by Araki, the bit error is corrected in this manner and the correction data is output through the out buffers 191 to 1916.
Next, FIG. 5 shows a block diagram of a semiconductor memory device disclosed by Sato. As shown in FIG. 5, the semiconductor memory device disclosed by Sato includes a ROM circuit 301, a defective address storage circuit 302, a fuse data holding circuit 303, a relief determination circuit 304, an ECC circuit 305, a data holding circuit 306, an address matching circuit 107, a switching holding circuit 308, and a switching circuit 309.
The ROM circuit 301 includes a memory data area 301a that holds necessary memory data, and a parity data area 301b that stores parity data for correcting an error of the memory data. The defective address storage circuit 302 stores a defective address which is an address of memory data determined as an error among memory data stored in the memory data area 301a. The fuse data holding circuit 303 holds fuse data output from the defective address storage circuit 302. The relief determination circuit 304 determines whether memory data determined as defective data is present or not, that is, whether it is necessary to relieve the data, based on the fuse data output from the fuse data holding circuit 303. The ECC circuit 305 corrects the memory data, which is determined as an error, based on parity data, and generates relief data corresponding to the defective address. The data holding circuit 306 stores the relief data generated by the ECC circuit 305. The address matching circuit 307 compares an input address input to read out the memory data, with the defective address. The switching holding circuit 308 holds the comparison result of the address matching circuit 307. When the input address matches the defective address as a result of the comparison by the address matching circuit 307, the switching circuit 309 outputs the relief data corresponding to the defective address. When the input address does not match the defective address, the switching circuit 309 outputs the memory data corresponding to the input address.
As described above, in the semiconductor memory device disclosed by Sato, the relief data generated by the ECC circuit 305 is output when the input address corresponds to the defective address, and the memory data corresponding to the input address is output when the input address does not correspond to the defective address. In this case, according to the technique disclosed by Sato, the relief data is generated at the time of start-up of the semiconductor memory device, thereby preventing the ECC circuit 305 from operating in the subsequent operation, and realizing an increase in speed of the subsequent operation.